Electronic technology today relies almost exclusively on crystalline silicon with compound semiconductors, such as GaAs, occupying small, but important, niches in optoelectronic and high speed applications. Amorphous silicon device configurations have rapidly progressed in both their performance and stability since the first report in 1979 by LeComber et al (Electronic Letters 15, 179 [1979]) of an amorphous silicon field effect transistor. Amorphous silicon technology has emerged as a prime candidate for large area thin film applications, first in photovoltaic applications and later in large area integrated circuits used in flat liquid crystal displays, solid state imagers, electronic copiers, printers and scanners. This semiconductor material is ideally suited for large area arrays(in excess of 12 inches by 12 inches) because the low deposition temperatures involved in its glow discharge fabrication process, make possible the use of inexpensive substrate materials, such as glass.
By comparison to crystalline silicon devices, the main difference with amorphous silicon devices is the relatively low electron band mobility (.ltoreq.20 cm.sup.2/ Vs) of the latter coupled with a relatively large density of localized states. This results in amorphous silicon devices having a slower switching time than single crystalline devices. However, in many large area applications, such as printing, since numerous operations can be performed in parallel, the overall system speed is quite fast. Futhermore, since amorphous silicon has a wide effective energy gap, an extremely large photoconductivity and good light senitivity, it is uniquely suited for optelectronic applications, particularly in the visible range.
In U.S. Pat. NO. 4,752,814 (Tuan) entitled "High Voltage Thin Film Transistor", assigned to the same assignee as the present application, there is taught a unique a-Si:H transitor device which may be operated at 500 volts, or more. In operation, several hundreds of volts can be switched by a low voltage gate signal. As with other amorphous silicon transistors, its fabrication process is simple and is compatible with other film devices. Several layers are sequentially deposited and patterned upon a substrate. An undoped or lightly doped, amorphous silicon charge transport layer is sandwiched between a conductive gate metal electrode and a gate dielectric layer, on one side, and n+ doped source and drain electrodes, on its other side. As described in this earlier patent, the device relies upon the face-to-face orientation of the gate electrode and the source electrode, in order that the gate electrode can control the injection of electrons flowing from the source into the charge transport layer. The electric field created by the insulated gate electrode attracts or repels electrons.
In U.S. Pat. No. 4,425,572 (Takafuji et al) entitled "Thin Film Transistor" there is disclosed a low voltage thin film transistor device having a gate electrode which does not extend fully between source and drain, in order to reduce voltage stress across the gate dielectric and to make the device more robust and less susceptible to dielectric breakdown. It should be noted that the charge transport layer is made of tellurium which supports ohmic current flow. Several prior art low voltage transistor configurations are illustrated in FIGS. 1-4, wherein the gate electrode is shown to fully span the channel between source and drain.
It is well known that in a high voltage, amorphous silicon, thin film transistor, of the type disclosed in the '814 patent, the gate electrode should not extend fully to the drain electrode, in order to maintain dielectric integrity. However, by offsetting the gate electrode, the degree of control over the OFF-state leakage current is diminished. The gate is less able to screen the source from the drain field. Furthermore, in such an amorphous silicon transistor wherein the charge transport layer between the source and drain includes a portion controlled by the gate (channel region) and a portion not controlled by the gate (dead region), current flow through the dead region will be space charge limited (SCLC). However, since the space charge limited leakage current varies superlinearly with the voltage imposed upon the drain electrode, one can expect leakage current at high drain voltages to be orders of magnitude higher than leakage current at low drain voltages. For example, if the drain electrode voltage is increased from 10 volts to 1000 volts, the space charge limited current would increase not by a factor of 100 (as with ohmic current), but closer to a factor of 10,000. Clearly this superlinearity exacerbates the source/drain leakage problem in high voltage devices of this type. For this reason, it was taught in the '814 patent that the requisite control of leakage current could only be achieved by the face-to-face orientation of the source electrode and gate electrode across the charge transport layer.
It is an object of this invention to provide a modified high voltage thin film transistor having a high ON/OFF ratio and effective leakage current suppression without sandwiching the source and gate electrodes in face-to-face relationship about the charge transport layer.